1. Field of the Invention
This invention relates to a semiconductor memory device capable of erasing simultaneously the data stored in a plurality of memory cells.
2. Description of the Related Art
One known nonvolatile semiconductor memory device capable of erasing all data simultaneously is a NAND flash memory. In a NAND flash memory, a plurality of memory cells and select gates arranged in the column direction are connected in series, thereby constituting one NAND cell. Each NAND cell is connected to the corresponding bit line via a select gate. For example, two adjacent bit lines are connected to a data storage circuit. The data storage circuit not only holds the write data externally supplied in writing the data but also holds the data read from the memory cell in reading the data.
In writing the data or reading the data, all of or half of the cells arranged in the row direction are written into or read from at a time. In an erase operation, when a high voltage is applied to a well region in which a memory cell array is formed and the word line for the selected cell is set to Vss and the word lines for the unselected cells are brought into the floating state, a high voltage is applied between the gate and well region of the selected cell. As a result, electrons escape from the floating gate into the substrate, with the result that the threshold voltage of the cell becomes negative. During the erase operation, the gates of the unselected cells are in the floating state. Accordingly, when the high voltage is applied to the well region, the voltages of the word lines also become high by coupling, with the result that the voltage between the gate and well regions of the selected cell does not become high, which prevents the data from being erased.
In the erase operation, the voltage of the well region where a memory cell is formed is made high, with the result that the voltage on the bit line connected to the drain of the memory cell becomes high. However, the data storage circuit connected to the bit line and the peripheral circuit for supplying a potential to the bit line are composed of low-voltage transistors incapable of withstanding a high voltage. Therefore, to protect the low-voltage transistors, a high-voltage transistor is connected between one end of the bit line and the data storage circuit and between the other end of the bit line and the peripheral circuit. In an erase operation, the transistors are turned off, thereby preventing the high voltage from being supplied to the data storage circuit and peripheral circuit.
As the elements are miniaturized further, low-voltage transistors are made smaller. However, high-voltage transistors are difficult to miniaturize. As the capacity of a semiconductor memory device is getting larger, the number of bit lines increases and therefore the number of high-voltage transistors connected to the bit lines increases, which becomes a problem. For example, a 4-Gbit NAND flash memory has 32K data storage circuits, which then include as many as 128K high-voltage transistors, four times the number of data storage circuits. The number of high-voltage transistors increases as the memory capacity increases. As a result, the percentage of high-voltage transistors occupying the chip becomes larger, which makes it difficult to reduce the chip area.
To overcome this difficulty, the technique for reducing the number of high-voltage transistors by connecting two high-voltage transistors equally to two bit lines (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 8-46159). By this technique, the number of high-voltage transistors can be halved as compared with a conventional equivalent. However, the technique has the following problem: as the memory capacity increases, the number of high-voltage transistors increases accordingly.